184 278

Cited 0 times in

저전력 디지털 보청기 프로세서 구현을 위한 distributed arithmetic 적응 필터 구조

Other Titles
 Distributed Arithmetic Adaptive Filter Structure for Low-power Digital Hearing Aid Processor Implementation 
Authors
 장영범  ;  이원상  ;  유선국 
Citation
 Transactions of the Korean Institute of Electrical Engineers (전기학회논문지), Vol.53D(9) : 657-662, 2004 
Journal Title
Transactions of the Korean Institute of Electrical Engineers(전기학회논문지)
ISSN
 1975-8359 
Issue Date
2004
Keywords
Distributed Arithmetic
Abstract
The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.
Files in This Item:
T200400505.pdf Download
Appears in Collections:
1. College of Medicine (의과대학) > Dept. of Medical Engineering (의학공학교실) > 1. Journal Papers
Yonsei Authors
Yoo, Sun Kook(유선국) ORCID logo https://orcid.org/0000-0002-6032-4686
URI
https://ir.ymlib.yonsei.ac.kr/handle/22282913/112247
사서에게 알리기
  feedback

qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse

Links