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J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications
DC Field | Value | Language |
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dc.contributor.author | 김민구 | - |
dc.date.accessioned | 2024-05-23T03:34:31Z | - |
dc.date.available | 2024-05-23T03:34:31Z | - |
dc.date.issued | 2024-04 | - |
dc.identifier.issn | 1936-0851 | - |
dc.identifier.uri | https://ir.ymlib.yonsei.ac.kr/handle/22282913/199256 | - |
dc.description.abstract | High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal–insulator–semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 105), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society. | - |
dc.description.statementOfResponsibility | restriction | - |
dc.language | English | - |
dc.publisher | American Chemical Society | - |
dc.relation.isPartOf | ACS NANO | - |
dc.rights | CC BY-NC-ND 2.0 KR | - |
dc.title | J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications | - |
dc.type | Article | - |
dc.contributor.college | College of Medicine (의과대학) | - |
dc.contributor.department | Dept. of Medical Engineering (의학공학교실) | - |
dc.contributor.googleauthor | Si Eun Yu | - |
dc.contributor.googleauthor | Han Joo Lee | - |
dc.contributor.googleauthor | Min-Gu Kim | - |
dc.contributor.googleauthor | Seongil Im | - |
dc.contributor.googleauthor | Young Tack Lee | - |
dc.identifier.doi | 10.1021/acsnano.4c01450 | - |
dc.contributor.localId | A06575 | - |
dc.relation.journalcode | J00005 | - |
dc.identifier.eissn | 1936-086X | - |
dc.identifier.pmid | 38629449 | - |
dc.identifier.url | https://pubs.acs.org/doi/10.1021/acsnano.4c01450 | - |
dc.subject.keyword | JFET | - |
dc.subject.keyword | MISFET | - |
dc.subject.keyword | hybrid dual-gate FET | - |
dc.subject.keyword | optoelectronic security logic system | - |
dc.subject.keyword | switchable logic | - |
dc.contributor.alternativeName | Kim, Min-Gu | - |
dc.contributor.affiliatedAuthor | 김민구 | - |
dc.citation.volume | 18 | - |
dc.citation.number | 17 | - |
dc.citation.startPage | 11404 | - |
dc.citation.endPage | 11415 | - |
dc.identifier.bibliographicCitation | ACS NANO, Vol.18(17) : 11404-11415, 2024-04 | - |
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